The fabrication of electronic circuitry wherein resistors and capacitors and their interconnections are formed by thin-film techniques is growing rapidly in importance. With thin-film technology, complex circuits having precision capacitors and resistors may be tailored to meet specific circuit design requirements, resulting in microcircuitry of reduced size, weight, and cost and increased reliability. One form of thin-film circuit, along with the method of manufacture, is disclosed in U.S. Pat. application Ser. No. 775,828 filed on Nov. 14, 1968, by George E. Bodway issued on Oct. 26, 1971, as U.S. Pat. No. 3,616,282 entitled METHOD OF PRODUCING THIN FILM CIRCUIT ELEMENTS, and assigned to the same assignee as the present patent application.
One typical process for the manufacture of thin film resistor-capacitor circuits of the type shown in U.S. Pat. No. 3,616,282 comprises the following steps, performed sequentially:
1. Forming the under-electrodes of the various capacitors on an insulating substrate by
A. sputtering a layer of conductive metal such as tantalum (Ta) over the surface of the substrate, PA1 B. forming a mask on the metal layer by a known photo-resist technique, and PA1 C. etching through the mask to remove all the metal except for the desired capacitor under electrodes and interconnections therebetween that serve to provide a single common electrical path for all the capacitor under electrodes during a subsequent anodizing step; PA1 A. depositing an oxide layer over the entire surface of the substrate, capacitor under electrodes, and interconnections, such as for example, by a silicon dioxide (SiO.sub.2) deposition, PA1 B. forming a mask on the oxide layer by the photo-resist technique, PA1 C. etching through the mask to remove the oxide layer from areas of the capacitor under-electrodes to be anodized, PA1 D. electrochemically anodizing the exposed portions of the capacitor under-electrodes in an appropriate electrolyte for an appropriate period of time to form the desired dielectric layer (for example, Ta.sub.2 O.sub.5) of each capacitor under-electrode, and PA1 e. removing the anodizing mask by an oxide etch, leaving the partially anodized under-electrodes and the interconnections therebetween; PA1 a. forming a mask by the photoresist technique leaving the interconnections exposed, and PA1 b. etching away the interconnections; PA1 a. sputtering a layer of resistive material such as (Ta.sub.2 N) over the entire surface of the substrate and capacitor electrodes, PA1 b. depositing a first layer of conductive material such as chrome gold (CrAu), which adheres well to the resistive layer, over the resistive layer, PA1 c. forming a mask, which covers those areas of the structure where the resistors are to remain, by the photoresist technique, and PA1 d. etching away the exposed first conductive layer and the underlying resistive layer, leaving the desired resistors; PA1 a. depositing a second layer of conductive material such as chrome gold (CrAu) over the entire surface of the structure, PA1 b. forming a mask, which covers those areas of the structure where the capacitor upper-electrodes and the underlying additional oxide layer are to remain, by the photoresist technique, and PA1 c. etching away the exposed second conductive layer and then the underlying additional oxide layer, leaving the desired capacitor upper-electrodes; PA1 a. depositing a third layer of conductive material such as chrome gold (CrAu) over the entire surface of the structure, PA1 b. forming a mask on the third conductive layer by the photoresist technique to define the capacitor upper-electrodes and interconnections, PA1 c. plating a thick layer (0.30-0.40 mils) of gold to form the interconnections, and PA1 d. etching away the second and then the third conductive layers where not covered by the thick gold interconnections.
2. Forming a dielectric layer over a portion of the surface of each of the capacitor under electrodes by
3. Removing the interconnections between the capacitor under-electrodes by
4. Forming the various resistors on the substrate by
5. In order to increase the yield of these circuits, depositing an additional oxide layer on the dielectric (Ta.sub.2 O.sub.5) layer of each capacitor under-electrode to cure pinholes therein and other imperfections produced therein during the various fabrication steps performed after the anodizing step, such as during the oxide etching step of 2(e) above and the resistive-layer sputtering step of 4(a) above, (this step is performed for example by depositing a layer of silicon dioxide (SiO.sub.2) for example over the structure with a value of .055 pf/mil.sup.2 .+-.5% for the combined Ta.sub.2 O.sub.5 and SiO.sub.2 layers).
6. Forming the upper-electrodes of various capacitors by
7. Completing the upper-electrodes of the various capacitors and forming the interconnections between the various capacitors and resistors by
It is noted that, in the above process, certain difficult steps are performed. For example, the masking and anodizing steps of 2(b), (c), and (d) above are troublesome since, during anodizing, the mask has to withstand 200 volts in an electrolytic bath, and the mask oftentimes breaks down.
Other difficult steps in the process are the interconnection masking and etching steps of 3(a) and (b) above. Still other difficult steps in the process are the making and etching steps of 6(b) and (c), particularly since the mask formed must be pinhole free to prevent pinholes from being etched in the capacitor dielectric layers. The etching step of 6(c) requires the use of a silicon dioxide in forming the additional oxide layer, since it is difficult or impossible to etch other forms of oxide layers, and only silicon dioxide has been found to be satisfactory.
Since a photoresist mask alone is not capable of withstanding the oxide etch needed to form the capacitors in the etching step of 6(c) the layer of CrAu deposited during the step of 6(a) is needed to serve as a mask, and thus the two layers of CrAu deposited during the steps of 6(a) and 7(a) and the two subsequent CrAu etching steps of 6(c) and 7(d) are needed.
Also, where silicon oxide layers are selectively etched and remaining portions thereof are subsequently gold plated through a masking, there is a tendency for an undesirable gold bead to form around the upper edges of the masked portions of the oxide layers, the mask being unable to adequately protect these edges.
Because of the high temperatures involved in the SiO.sub.2 deposition step of 5 above, it is necessary that the first layer of CrAu deposited in the step of 4(b) above be fairly thick, so as not to be deleteriously affected by diffusion of chrome therefrom due to the heat. Consequently, the etching step of 4(d) above is lengthened resulting in less than optimum resistor definition.
The above process requires seven masking steps, and the trips between the photoresist masking stages and the subsequent deposition and etching stages result in an overall fabrication period of approximately 3 weeks.